Changeset 260 for HW_tools/sff_sdr/serial_loader/trunk/DVFlasher
- Timestamp:
- 08/20/08 17:18:03 (5 months ago)
- Location:
- HW_tools/sff_sdr/serial_loader/trunk/DVFlasher
- Files:
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- 11 modified
- 4 moved
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DVFlasher/DVFlasher.cs (modified) (1 diff)
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DVFlasher/Makefile (moved) (moved from HW_tools/sff_sdr/serial_loader/trunk/DVFlasher/DVFlasher/makefile) (1 diff)
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Makefile (moved) (moved from HW_tools/sff_sdr/serial_loader/trunk/DVFlasher/makefile)
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ubl/Makefile (moved) (moved from HW_tools/sff_sdr/serial_loader/trunk/DVFlasher/ubl/makefile)
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ubl/include/uart.h (modified) (2 diffs)
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ubl/include/ubl.h (modified) (1 diff)
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ubl/src/Makefile (moved) (moved from HW_tools/sff_sdr/serial_loader/trunk/DVFlasher/ubl/src/makefile)
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ubl/src/nand.c (modified) (10 diffs)
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ubl/src/nandboot.c (modified) (4 diffs)
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ubl/src/nor.c (modified) (43 diffs)
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ubl/src/norboot.c (modified) (1 diff)
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ubl/src/uart.c (modified) (3 diffs)
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ubl/src/uartboot.c (modified) (4 diffs)
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ubl/src/ubl.c (modified) (6 diffs)
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ubl/src/util.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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HW_tools/sff_sdr/serial_loader/trunk/DVFlasher/DVFlasher/DVFlasher.cs
r198 r260 276 276 myCmdParams.UARTUBLUsed = true; 277 277 278 myCmdParams.NORUBLExecAddr = 0x2 aa0;279 myCmdParams.NANDUBLExecAddr = 0x2 6ec;278 myCmdParams.NORUBLExecAddr = 0x29c8; 279 myCmdParams.NANDUBLExecAddr = 0x259c; 280 280 281 281 myCmdParams.APPMagicFlag = MagicFlags.UBL_MAGIC_SAFE; -
HW_tools/sff_sdr/serial_loader/trunk/DVFlasher/DVFlasher/Makefile
r246 r260 11 11 # v1.11 on 07-Mar-2007 12 12 # v1.12 on 14-Mar-2007 13 VER=1_14 13 VER=1_14_1 14 14 15 15 MONOCOMPILE=gmcs -
HW_tools/sff_sdr/serial_loader/trunk/DVFlasher/ubl/include/uart.h
r259 r260 19 19 #define MAXSTRLEN 256 20 20 21 typedef struct _UART_ACK_HEADER {22 uint32_tmagicNum;23 uint32_tappStartAddr;24 uint32_tsrecByteCnt;25 uint32_tsrecAddr;26 uint32_tbinByteCnt;27 uint32_tbinAddr;21 typedef struct _UART_ACK_HEADER { 22 uint32_t magicNum; 23 uint32_t appStartAddr; 24 uint32_t srecByteCnt; 25 uint32_t srecAddr; 26 uint32_t binByteCnt; 27 uint32_t binAddr; 28 28 } UART_ACK_HEADER; 29 29 … … 33 33 34 34 // Simple send/recv functions 35 uint32_t UARTSendData(uint8_t *seq, Bool includeNull); 36 uint32_t UARTSendInt(uint32_t value); 37 int32_t GetStringLen(uint8_t *seq); 35 void UARTSendCRLF(void); 36 void UARTSendString(char *string); 37 void UARTSendStringCRLF(char *string); 38 void UARTSendStringNULL(char *string); 39 void UARTSendInt(uint32_t value); 38 40 uint32_t UARTRecvData(uint32_t numBytes, uint8_t *seq); 39 41 -
HW_tools/sff_sdr/serial_loader/trunk/DVFlasher/ubl/include/ubl.h
r259 r260 23 23 #include "tistdtypes.h" 24 24 25 / /UBL version number26 #define UBL_VERSION_STRING "1.1 2.1"25 /* UBL version number */ 26 #define UBL_VERSION_STRING "1.13" 27 27 #ifdef UBL_NAND 28 28 #define UBL_FLASH_TYPE "NAND" -
HW_tools/sff_sdr/serial_loader/trunk/DVFlasher/ubl/src/nand.c
r259 r260 1 1 /* -------------------------------------------------------------------------- 2 FILE : nand.c3 4 5 6 DATE: Jan-22-20077 8 9 v1.0 completion10 11 12 13 14 15 16 ----------------------------------------------------------------------------- */2 * FILE : nand.c 3 * PURPOSE : NAND driver file 4 * PROJECT : DaVinci User Boot-Loader and Flasher 5 * AUTHOR : Daniel Allred 6 * DATE : Jan-22-2007 7 * 8 * HISTORY 9 * v1.0 completion 10 * Daniel Allred - Jan-22-2007 11 * v1.11 DJA - Mar-07-2007 12 * Fixed bug(s) for writing and reading Big BLock (2K) NAND devices. 13 * v1.12 DJA - Mar-14-2007 14 * Fixed bug for writing 256/512 block devices caused by v1.11 update 15 * (Thanks to Ivan Tonchev) 16 * -------------------------------------------------------------------------- */ 17 17 18 18 #ifdef UBL_NAND … … 25 25 26 26 /* Define this to have more verbose debug messages */ 27 //#define NAND_DEBUG 1 27 #undef NAND_DEBUG 28 28 29 29 static uint8_t gNandTx[MAX_PAGE_SIZE] __attribute__((section(".ddrram2"))); 30 30 static uint8_t gNandRx[MAX_PAGE_SIZE] __attribute__((section(".ddrram2"))); 31 31 32 / / Symbol from linker script32 /* Symbol from linker script */ 33 33 extern uint32_t __NANDFlash; 34 34 35 / / structure for holding details about the NAND device itself35 /* structure for holding details about the NAND device itself */ 36 36 volatile NAND_INFO gNandInfo; 37 37 38 / / Table of ROM supported NAND devices39 const NAND_DEVICE_INFO gNandDevInfo[] = 40 { // devID, numBlocks, pagesPerBlock, bytesPerPage 41 {0x6E, 256, 16, 256+8}, /*1 MB */42 {0x68, 256, 16, 256+8}, /*1 MB */43 {0xEC, 256, 16, 256+8}, /*1 MB */44 {0xE8, 256, 16, 256+8}, /*1 MB */45 {0xEA, 512, 16, 256+8}, /*2 MB */46 {0xE3, 512, 16, 512+16}, /*4 MB */47 {0xE5, 512, 16, 512+16}, /*4 MB */48 {0xE6, 1024, 16, 512+16}, /*8 MB */49 {0x39, 1024, 16, 512+16}, /*8 MB */50 {0x6B, 1024, 16, 512+16}, /*8 MB */51 {0x73, 1024, 32, 512+16}, /*16 MB */52 {0x33, 1024, 32, 512+16}, /*16 MB */53 {0x75, 2048, 32, 512+16}, /*32 MB */54 {0x35, 2048, 32, 512+16}, /*32 MB */55 {0x43, 1024, 32, 512+16}, /*16 MB 0x1243 */56 {0x45, 2048, 32, 512+16}, /*32 MB 0x1245 */57 {0x53, 1024, 32, 512+16}, /*16 MB 0x1253 */58 {0x55, 2048, 32, 512+16}, /*32 MB 0x1255 */59 {0x36, 4096, 32, 512+16}, /*64 MB */60 {0x46, 4096, 32, 512+16}, /*64 MB 0x1346 */61 {0x56, 4096, 32, 512+16}, /*64 MB 0x1356 */62 {0x76, 4096, 32, 512+16}, /*64 MB */63 {0x74, 8192, 32, 512+16},/* 128 MB 0x1374 */64 {0x79, 8192, 32, 512+16},/* 128 MB */65 {0x71, 16384, 32, 512+16},/* 256 MB */66 {0xF1, 1024, 64, 2048+64},/* 128 MB - Big Block */67 {0xA1, 1024, 64, 2048+64},/* 128 MB - Big Block */68 {0xAA, 2048, 64, 2048+64},/* 256 MB - Big Block */69 {0xDA, 2048, 64, 2048+64},/* 256 MB - Big Block */70 {0xDC, 4096, 64, 2048+64},/* 512 MB - Big Block */71 {0xAC, 4096, 64, 2048+64},/* 512 MB - Big Block */72 {0xB1, 1024, 64, 2048+64},/* 128 MB - Big Block 0x22B1 */73 {0xC1, 1024, 64, 2048+64},/* 128 MB - Big Block 0x22C1 */74 {0x00, 0, 0, 0} /* Dummy null entry to indicate end of table*/38 /* Table of ROM supported NAND devices */ 39 const NAND_DEVICE_INFO gNandDevInfo[] = { 40 /* devID, numBlocks, pagesPerBlock, bytesPerPage */ 41 {0x6E, 256, 16, 256+8}, /* 1 MB */ 42 {0x68, 256, 16, 256+8}, /* 1 MB */ 43 {0xEC, 256, 16, 256+8}, /* 1 MB */ 44 {0xE8, 256, 16, 256+8}, /* 1 MB */ 45 {0xEA, 512, 16, 256+8}, /* 2 MB */ 46 {0xE3, 512, 16, 512+16}, /* 4 MB */ 47 {0xE5, 512, 16, 512+16}, /* 4 MB */ 48 {0xE6, 1024, 16, 512+16}, /* 8 MB */ 49 {0x39, 1024, 16, 512+16}, /* 8 MB */ 50 {0x6B, 1024, 16, 512+16}, /* 8 MB */ 51 {0x73, 1024, 32, 512+16}, /* 16 MB */ 52 {0x33, 1024, 32, 512+16}, /* 16 MB */ 53 {0x75, 2048, 32, 512+16}, /* 32 MB */ 54 {0x35, 2048, 32, 512+16}, /* 32 MB */ 55 {0x43, 1024, 32, 512+16}, /* 16 MB 0x1243 */ 56 {0x45, 2048, 32, 512+16}, /* 32 MB 0x1245 */ 57 {0x53, 1024, 32, 512+16}, /* 16 MB 0x1253 */ 58 {0x55, 2048, 32, 512+16}, /* 32 MB 0x1255 */ 59 {0x36, 4096, 32, 512+16}, /* 64 MB */ 60 {0x46, 4096, 32, 512+16}, /* 64 MB 0x1346 */ 61 {0x56, 4096, 32, 512+16}, /* 64 MB 0x1356 */ 62 {0x76, 4096, 32, 512+16}, /* 64 MB */ 63 {0x74, 8192, 32, 512+16}, /* 128 MB 0x1374 */ 64 {0x79, 8192, 32, 512+16}, /* 128 MB */ 65 {0x71, 16384, 32, 512+16}, /* 256 MB */ 66 {0xF1, 1024, 64, 2048+64}, /* 128 MB - Big Block */ 67 {0xA1, 1024, 64, 2048+64}, /* 128 MB - Big Block */ 68 {0xAA, 2048, 64, 2048+64}, /* 256 MB - Big Block */ 69 {0xDA, 2048, 64, 2048+64}, /* 256 MB - Big Block */ 70 {0xDC, 4096, 64, 2048+64}, /* 512 MB - Big Block */ 71 {0xAC, 4096, 64, 2048+64}, /* 512 MB - Big Block */ 72 {0xB1, 1024, 64, 2048+64}, /* 128 MB - Big Block 0x22B1 */ 73 {0xC1, 1024, 64, 2048+64}, /* 128 MB - Big Block 0x22C1 */ 74 {0x00, 0, 0, 0} /* Null entry to indicate end of table */ 75 75 }; 76 76 77 volatile uint8_t *flash_make_addr 78 { 79 return ((volatile uint8_t *) ( baseAddr + offset));77 volatile uint8_t *flash_make_addr(uint32_t baseAddr, uint32_t offset) 78 { 79 return ((volatile uint8_t *) (baseAddr + offset)); 80 80 } 81 81 … … 86 86 dataword.l = data; 87 87 88 addr.cp = flash_make_addr (pNandInfo->flashBase, offset); 89 switch (pNandInfo->busWidth) 90 { 91 case BUS_8BIT: 92 *addr.cp = dataword.c; 93 break; 94 case BUS_16BIT: 95 *addr.wp = dataword.w; 96 break; 97 } 98 } 99 100 void flash_write_cmd (PNAND_INFO pNandInfo, uint32_t cmd) 88 addr.cp = flash_make_addr(pNandInfo->flashBase, offset); 89 switch (pNandInfo->busWidth) { 90 case BUS_8BIT: 91 *addr.cp = dataword.c; 92 break; 93 case BUS_16BIT: 94 *addr.wp = dataword.w; 95 break; 96 } 97 } 98 99 void flash_write_cmd(PNAND_INFO pNandInfo, uint32_t cmd) 101 100 { 102 101 flash_write_data(pNandInfo, NAND_CLE_OFFSET, cmd); 103 102 } 104 103 105 void flash_write_addr 104 void flash_write_addr(PNAND_INFO pNandInfo, uint32_t addr) 106 105 { 107 106 flash_write_data(pNandInfo, NAND_ALE_OFFSET, addr); 108 107 } 109 108 110 void flash_write_bytes(PNAND_INFO pNandInfo, void *pSrc, uint32_t numBytes)111 { 112 109 void flash_write_bytes(PNAND_INFO pNandInfo, void *pSrc, uint32_t numBytes) 110 { 111 volatile FLASHPtr destAddr, srcAddr; 113 112 uint32_t i; 114 113 115 114 srcAddr.cp = (volatile uint8_t*) pSrc; 116 destAddr.cp = flash_make_addr (pNandInfo->flashBase, NAND_DATA_OFFSET ); 117 switch (pNandInfo->busWidth) 118 { 119 case BUS_8BIT: 120 for(i=0;i<( numBytes );i++) 121 *destAddr.cp = *srcAddr.cp++; 122 break; 123 case BUS_16BIT: 124 for(i=0;i<( numBytes >> 1);i++) 125 *destAddr.wp = *srcAddr.wp++; 126 break; 127 } 128 129 } 130 131 void flash_write_addr_cycles(PNAND_INFO pNandInfo, uint32_t block, uint32_t page) 132 { 133 flash_write_addr_bytes(pNandInfo, pNandInfo->numColAddrBytes, 0x00000000); 134 flash_write_row_addr_bytes(pNandInfo, block, page); 135 } 136 137 void flash_write_addr_bytes(PNAND_INFO pNandInfo, uint32_t numAddrBytes, uint32_t addr) 138 { 139 uint32_t i; 140 for (i=0; i<numAddrBytes; i++) 141 { 142 flash_write_addr(pNandInfo, ( (addr >> (8*i) ) & 0xff) ); 143 } 144 } 145 146 void flash_write_row_addr_bytes(PNAND_INFO pNandInfo, uint32_t block, uint32_t page) 147 { 148 uint32_t row_addr; 149 row_addr = (block << (pNandInfo->blkShift - pNandInfo->pageShift)) | page; 115 destAddr.cp = flash_make_addr(pNandInfo->flashBase, NAND_DATA_OFFSET); 116 switch (pNandInfo->busWidth) { 117 case BUS_8BIT: 118 for (i = 0; i < numBytes; i++) 119 *destAddr.cp = *srcAddr.cp++; 120 break; 121 case BUS_16BIT: 122 for (i = 0; i < (numBytes >> 1); i++) 123 *destAddr.wp = *srcAddr.wp++; 124 break; 125 } 126 } 127 128 void flash_write_addr_cycles(PNAND_INFO pNandInfo, uint32_t block, 129 uint32_t page) 130 { 131 flash_write_addr_bytes(pNandInfo, pNandInfo->numColAddrBytes, 132 0x00000000); 133 flash_write_row_addr_bytes(pNandInfo, block, page); 134 } 135 136 void flash_write_addr_bytes(PNAND_INFO pNandInfo, uint32_t numAddrBytes, 137 uint32_t addr) 138 { 139 uint32_t i; 140 for (i = 0; i < numAddrBytes; i++) 141 flash_write_addr(pNandInfo, ((addr >> (8*i)) & 0xff)); 142 } 143 144 void flash_write_row_addr_bytes(PNAND_INFO pNandInfo, uint32_t block, 145 uint32_t page) 146 { 147 uint32_t row_addr; 148 row_addr = 149 (block << (pNandInfo->blkShift - pNandInfo->pageShift)) | page; 150 150 flash_write_addr_bytes(pNandInfo, pNandInfo->numRowAddrBytes, row_addr); 151 151 } 152 152 153 uint32_t flash_read_data 153 uint32_t flash_read_data(PNAND_INFO pNandInfo) 154 154 { 155 155 volatile FLASHPtr addr; … … 157 157 cmdword.l = 0x0; 158 158 159 addr.cp = flash_make_addr (pNandInfo->flashBase, NAND_DATA_OFFSET ); 160 switch (gNandInfo.busWidth) 161 { 162 case BUS_8BIT: 163 cmdword.c = *addr.cp; 164 break; 165 case BUS_16BIT: 166 cmdword.w = *addr.wp; 167 break; 159 addr.cp = flash_make_addr(pNandInfo->flashBase, NAND_DATA_OFFSET); 160 switch (gNandInfo.busWidth) { 161 case BUS_8BIT: 162 cmdword.c = *addr.cp; 163 break; 164 case BUS_16BIT: 165 cmdword.w = *addr.wp; 166 break; 168 167 } 169 168 return cmdword.l; 170 169 } 171 170 172 void flash_read_bytes(PNAND_INFO pNandInfo, void *pDest, uint32_t numBytes)173 { 174 171 void flash_read_bytes(PNAND_INFO pNandInfo, void *pDest, uint32_t numBytes) 172 { 173 volatile FLASHPtr destAddr, srcAddr; 175 174 uint32_t i; 176 175 177 176 destAddr.cp = (volatile uint8_t*) pDest; 178 srcAddr.cp = flash_make_addr (pNandInfo->flashBase, NAND_DATA_OFFSET ); 179 switch (pNandInfo->busWidth) 180 { 181 case BUS_8BIT: 182 for(i=0;i<( numBytes );i++) 183 *destAddr.cp++ = *srcAddr.cp; 184 break; 185 case BUS_16BIT: 186 for(i=0;i<( numBytes >> 1);i++) 187 *destAddr.wp++ = *srcAddr.wp; 188 break; 189 } 190 } 191 192 void flash_swap_data(PNAND_INFO pNandInfo, uint32_t* data) 193 { 194 uint32_t i,temp = *data; 195 volatile FLASHPtr dataAddr, tempAddr; 196 197 dataAddr.cp = flash_make_addr((uint32_t) data, 3); 198 tempAddr.cp = flash_make_addr((uint32_t) &temp,0); 199 200 switch (gNandInfo.busWidth) 201 { 202 case BUS_8BIT: 203 for(i=0; i<4; i++) 204 *dataAddr.cp-- = *tempAddr.cp++; 205 break; 206 case BUS_16BIT: 207 for(i=0; i<2; i++) 208 *dataAddr.wp-- = *tempAddr.wp++; 209 break; 210 } 211 } 212 213 // Poll bit of NANDFSR to indicate ready 214 uint32_t NAND_WaitForRdy(uint32_t timeout) { 177 srcAddr.cp = flash_make_addr(pNandInfo->flashBase, NAND_DATA_OFFSET); 178 switch (pNandInfo->busWidth) { 179 case BUS_8BIT: 180 for (i = 0; i < numBytes; i++) 181 *destAddr.cp++ = *srcAddr.cp; 182 break; 183 case BUS_16BIT: 184 for (i = 0; i < (numBytes >> 1); i++) 185 *destAddr.wp++ = *srcAddr.wp; 186 break; 187 } 188 } 189 190 void flash_swap_data(PNAND_INFO pNandInfo, uint32_t *data) 191 { 192 uint32_t i, temp = *data; 193 volatile FLASHPtr dataAddr, tempAddr; 194 195 dataAddr.cp = flash_make_addr((uint32_t) data, 3); 196 tempAddr.cp = flash_make_addr((uint32_t) &temp, 0); 197 198 switch (gNandInfo.busWidth) { 199 case BUS_8BIT: 200 for (i = 0; i < 4; i++) 201 *dataAddr.cp-- = *tempAddr.cp++; 202 break; 203 case BUS_16BIT: 204 for (i = 0; i < 2; i++) 205 *dataAddr.wp-- = *tempAddr.wp++; 206 break; 207 } 208 } 209 210 /* Poll bit of NANDFSR to indicate ready */ 211 uint32_t NAND_WaitForRdy(uint32_t timeout) 212 { 215 213 volatile uint32_t cnt; 216 214 cnt = timeout; … … 218 216 waitloop(200); 219 217 220 while ( !(AEMIF->NANDFSR & NAND_NANDFSR_READY) && ((cnt--) > 0))221 222 if(cnt == 0) 223 {224 UARTSendData((uint8_t *)"NANDWaitForRdy() Timeout!\n", FALSE);225 return E_FAIL; 226 } 227 228 #ifdef NAND_DEBUG 229 UARTSendData((uint8_t *) "NANDWaitForRdy()Remaining time = ", FALSE);230 UARTSendInt(cnt); 231 UARTSendData((uint8_t *) "\r\n", FALSE); 232 #endif 233 234 return E_PASS; 235 } 236 237 238 // Wait for the status to be ready in NAND register 239 // There were some problems reported in DM320 with Ready/Busy pin 240 // not working with all NANDs. So this check has also been added. 241 uint32_t NAND_WaitForStatus(uint32_t timeout){218 while (!(AEMIF->NANDFSR & NAND_NANDFSR_READY) && ((cnt--) > 0)) 219 if (cnt == 0) { 220 UARTSendString("NANDWaitForRdy() Timeout!\n"); 221 return E_FAIL; 222 } 223 224 #ifdef NAND_DEBUG 225 UARTSendString("NANDWaitForRdy()Remaining time = "); 226 UARTSendInt(cnt); 227 UARTSendCRLF(); 228 #endif 229 230 return E_PASS; 231 } 232 233 234 /* Wait for the status to be ready in NAND register 235 * There were some problems reported in DM320 with Ready/Busy pin 236 * not working with all NANDs. So this check has also been added. 237 */ 238 uint32_t NAND_WaitForStatus(uint32_t timeout) 239 { 242 240 volatile uint32_t cnt; 243 241 uint32_t status; 244 242 cnt = timeout; 245 243 246 do 247 { 248 flash_write_cmd((PNAND_INFO)&gNandInfo,NAND_STATUS); 249 status = flash_read_data((PNAND_INFO)&gNandInfo) & (NAND_STATUS_ERROR | NAND_STATUS_BUSY); 250 cnt--; 251 } 252 while((cnt>0) && !status); 253 254 if(cnt == 0) 255 { 256 UARTSendData((uint8_t *)"NANDWaitForStatus() Timeout!\n", FALSE); 244 do { 245 flash_write_cmd((PNAND_INFO)&gNandInfo, NAND_STATUS); 246 status = flash_read_data((PNAND_INFO)&gNandInfo) & 247 (NAND_STATUS_ERROR | NAND_STATUS_BUSY); 248 cnt--; 249 } 250 while ((cnt > 0) && !status); 251 252 if (cnt == 0) { 253 UARTSendString("NANDWaitForStatus() Timeout!\n"); 257 254 return E_FAIL; 258 255 } … … 261 258 } 262 259 263 // Read the current ECC calculation and restart process 264 uint32_t NAND_ECCReadAndRestart (PNAND_INFO pNandInfo) 265 { 266 uint32_t retval; 267 // Read and mask appropriate (based on CSn space flash is in) ECC register 268 retval = ((uint32_t*)(&(AEMIF->NANDF1ECC)))[pNandInfo->CSOffset] & pNandInfo->ECCMask; 269 270 waitloop(5); 271 272 #ifdef NAND_DEBUG 273 UARTSendData((uint8_t *)"Value read from ECC register = ", FALSE); 274 UARTSendInt(retval); 275 UARTSendData((uint8_t *)"\r\n", FALSE); 276 UARTSendData((uint8_t *)".", FALSE); 277 #endif 278 279 // Write appropriate bit to start ECC calculations 280 AEMIF->NANDFCR |= (1<<(8 + (pNandInfo->CSOffset))); 281 return retval; 282 } 283 284 // Initialize NAND interface and find the details of the NAND used 260 /* Read the current ECC calculation and restart process */ 261 uint32_t NAND_ECCReadAndRestart(PNAND_INFO pNandInfo) 262 { 263 uint32_t retval; 264 /* Read and mask appropriate (based on CSn space flash is in) 265 * ECC register */ 266 retval = ((uint32_t *)(&(AEMIF->NANDF1ECC)))[pNandInfo->CSOffset] & 267 pNandInfo->ECCMask; 268 269 waitloop(5); 270 271 #ifdef NAND_DEBUG 272 UARTSendString("Value read from ECC register = "); 273 UARTSendInt(retval); 274 UARTSendCRLF(); 275 UARTSendString("."); 276 #endif 277 278 /* Write appropriate bit to start ECC calculations */ 279 AEMIF->NANDFCR |= (1<<(8 + (pNandInfo->CSOffset))); 280 return retval; 281 } 282 283 /* Initialize NAND interface and find the details of the NAND used */ 285 284 uint32_t NAND_Init() 286 285 { 287 uint32_t width, *CSRegs; 288 289 UARTSendData((uint8_t *) "Initializing NAND flash:\r\n", FALSE); 290 291 // Set NAND flash base address 292 gNandInfo.flashBase = (uint32_t) &(__NANDFlash); 293 294 //Get the CSOffset (can be 0 through 3 - corresponds with CS2 through CS5) 295 gNandInfo.CSOffset = (gNandInfo.flashBase >> 25) - 1; 296 297 // Setting the nand_width = 0(8 bit NAND) or 1(16 bit NAND). AEMIF CS2 bus Width 298 // is given by the BOOTCFG(bit no.5) 299 width = (((SYSTEM->BOOTCFG) & 0x20) >> 5); 300 gNandInfo.busWidth = (width)?BUS_16BIT:BUS_8BIT; 301 302 // Setup AEMIF registers for NAND 303 CSRegs = (uint32_t*) &(AEMIF->AB1CR); 304 CSRegs[gNandInfo.CSOffset] = 0x3FFFFFFC | width; // Set correct ABxCR reg 305 AEMIF->NANDFCR |= (0x1 << (gNandInfo.CSOffset)); // NAND enable for CSx 306 NAND_ECCReadAndRestart((PNAND_INFO)&gNandInfo); 307 308 // Send reset command to NAND 309 flash_write_cmd( (PNAND_INFO)&gNandInfo, NAND_RESET ); 310 311 if ( NAND_WaitForRdy(NAND_TIMEOUT) != E_PASS ) 312 return E_FAIL; 313 286 uint32_t width, *CSRegs; 287 288 UARTSendString("Initializing NAND flash:\r\n"); 289 290 /* Set NAND flash base address */ 291 gNandInfo.flashBase = (uint32_t) &(__NANDFlash); 292 293 /* Get the CSOffset (can be 0 through 3 - corresponds with CS2 through 294 * CS5) */ 295 gNandInfo.CSOffset = (gNandInfo.flashBase >> 25) - 1; 296 297 /* Setting the nand_width = 0(8 bit NAND) or 1(16 bit NAND). AEMIF CS2 298 * bus Width is given by the BOOTCFG(bit no.5). */ 299 width = (((SYSTEM->BOOTCFG) & 0x20) >> 5); 300 gNandInfo.busWidth = (width)?BUS_16BIT:BUS_8BIT; 301 302 /* Setup AEMIF registers for NAND */ 303 CSRegs = (uint32_t *) &(AEMIF->AB1CR); 304 305 /* Set correct ABxCR reg */ 306 CSRegs[gNandInfo.CSOffset] = 0x3FFFFFFC | width; 307 308 /* NAND enable for CSx. */ 309 AEMIF->NANDFCR |= (0x1 << (gNandInfo.CSOffset));